Senior FPGA Engineer

Job description:

This is a HYBRID role

We are seeking a talented senior engineer to join the digital design.
The successful candidate will contribute to FPGA development with an emphasis on validation and test/support.
Candidate must have experience using high level design, simulation and verification tools and be familiar with process flows supporting design and verification for digital FPGA efforts.
Preference will be given to candidates with an understanding of sensor control, filter design and algorithm implementation in hardware.
Direct experience with embedded FPGA design is required.

Required Qualifications:
BSEE with 6 years relevant experience
Fluent in SystemVerilog/VHDL
Experience with Xiliinx Vivado design tools
Implementation of fixed-point arithmetic, filter design, algorithm design and other DSP functions
Ability to debug designs simulated in a UVM environment
Experience with git and other version control systems
Experience with design closure including timing, power and area for SWaP constrained designs
Strong lab-debugging experience, including use of Xilinx integrated logic analyzers (ILAs) and experience with common test equipment such as oscilloscopes, digital multi-meters and logic analyzers.
Strong analysis and problem solving skills
Required to be on-site at least 4 days/week initially

Preferred Qualifications:

MSEE with 6 years relevant experience
Experience with Linux and scripting languages
Experience integrating FPGAs with sensors in-the-loop
Experience with control theory and/or design and implementation of control loops
Experience with bug tracking and continuous integration / continuous development (CI/CD)
UVM skills (Test and/or Test Bench development)
Experience with Matlab/Simulink
Experience working with PCB designers
Active US secret/TS clearance strongly preferred

Security Requirement:
Applicants selected for this position will be required to obtain and maintain a government security clearance.
Current in scope Secret or Top Secret strongly preferred.

Qualifications:

Required Qualifications:
BSEE with 6 years relevant experience
Fluent in SystemVerilog/VHDL
Experience with Xiliinx Vivado design tools
Implementation of fixed-point arithmetic, filter design, algorithm design and other DSP functions
Ability to debug designs simulated in a UVM environment
Experience with git and other version control systems
Experience with design closure including timing, power and area for SWaP constrained designs
Strong lab-debugging experience, including use of Xilinx integrated logic analyzers (ILAs) and experience with common test equipment such as oscilloscopes, digital multi-meters and logic analyzers.
Strong analysis and problem solving skills
Required to be on-site at least 4 days/week initially

Preferred Qualifications:

MSEE with 6 years relevant experience
Experience with Linux and scripting languages
Experience integrating FPGAs with sensors in-the-loop
Experience with control theory and/or design and implementation of control loops
Experience with bug tracking and continuous integration / continuous development (CI/CD)
UVM skills (Test and/or Test Bench development)
Experience with Matlab/Simulink
Experience working with PCB designers
Active US secret/TS clearance strongly preferred

Security Requirement:
Applicants selected for this position will be required to obtain and maintain a government security clearance.
Current in scope Secret or Top Secret strongly preferred.

Why is This a Great Opportunity:

We are seeking a talented senior engineer to join the digital design.
The successful candidate will contribute to FPGA development with an emphasis on validation and test/support.

Salary Type : Annual Salary

Salary Min : 150000

Salary Max : 165000

Currency Type : US Dollars