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Staff FPGA Logic Design Engineer

200,000 – 270,000 yearly

NPAworldwide Recruitment Network

Last Updated: 10/01/22

Job Description

Job description:

Staff Logic Design Engineer-Bay Area California

Our client is a leader in the test and measurement industry and has a long history of innovation and technology leadership. For many years they have been designing custom electronics to meet the unique and challenging requirements of their products. They offer a stimulating fast-paced environment where everyone is a contributor. The staff FPGA logic design engineer will play a key role in full product lifecycle design. If you want to be an impact player and work with other extremely talented engineers, this might be the place for you. Onsite daily is preferred, but hybrid with limited time in office will be considered.

Position Summary and Responsibilities

There are 2 open positions- one FPGA transceiver focused, the other is general FPGA. Both are staff level and will be responsible for entire logic/FPGA design lifecycle- architecture, logic design, simulation, test, and build. These roles require design of complex logic- not just integration. Experience with network protocols is preferred.

Design and test FPGA circuitry for next generation products:

  • Define logic architecture of various blocks of the design
  • Design blocks using Verilog, verify their block level functionality through simulation
  • Document the design, review with the rest of the team
  • Drive FPGA tools to compile the code and ensure timing closure
  • Verify proper operation of your circuit via system level test with test hardware
  • Work with the verification engineer to validate your circuit in a whole chip simulation environment

Work with customer support to reproduce and fix issues found in the field:

  • Reproduce customer environment to reproduce any failures found in the field
  • Fix the RTL, recompile the FPGA and review the changes with the team


  • BS in EE, CE or CS; MS or PhD preferred
  • 5-10 years of FPGA design experience (some ASIC experience is OK)
  • Knowledge of FPGA tools such as Quartus, Vivado, Modelsim, Signal tap, and Chipscope.
  • Ability to write timing constraints and designs that repeatedly achieve timing closure
  • Stronginterpersonal, organizational and communication skills; team player,persuasive, encouraging, and motivating; open minded, quick learner, creative, likes challenges; experience working both independently and in a team-oriented, collaborative environment; ability to effectively prioritize and execute tasks in a high-pressure environment.


  • Experience with Monitoring and/or Test & Measurement tools
  • Experience with one or more of the following protocols: PCIe, CXL, NVMe, USB, SAS, SATA
Why is This a Great Opportunity:

stable company, very low turnover, great technology and work environment

Salary Type : Annual Salary

Salary Min : 200000

Salary Max : 270000

Currency Type : US Dollars

Company Details

Grand Rapids, Michigan, United States
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